1. Field of the Invention
The present invention relates to a signal detecting circuit, and particularly to a signal detecting circuit for detecting a differential signal of a minute amplitude.
2. Description of the Background Art
In a data communications field, signals are transmitted at high speed. Differential signals of small amplitudes are used as transmission signals for fast transmission and low current consumption. The differential signal is formed of a pair of complementary signals, which are set to high and low levels relative to a reference potential, respectively. Such differential signal has a signal amplitude doubled as compared with the case of transferring a single signal, and therefore, the differential signal is usually used as the transmission signal in fast digital communications.
In data transmission, synchronization of data must be established between transmission and reception sides. A clock signal is used for establishing such synchronization. As a kind of method for transmitting a clock signal, there has been a method in which a clock signal for synchronization is transferred from a transmission side to a reception side through a signal line other than a signal line for data, or in which a clock signal is embedded in a transmission data string for transmission to a reception side. In the clock-embedded method such as an 8b/10b method, the clock signal is extracted from a received data string, and is reproduced on the reception side. In this clock embedded method, when data is not transferred, data of a predetermined pattern is repetitively transferred for determining whether the data is being transferred or not. For example, in a frame synchronization method, a predetermined flag pattern is repetitively transmitted and received when a digital signal is not transmitted or received.
In the 8b/10b method or the like in which a differential signal is serially transferred as data, a digital signal line pair is kept at a reference voltage level of an intermediate voltage while transmission and reception are not performed, even when a data transmission path is in a normal state. When potentials of complementary signal lines of the transmission path are different from the reference potential, it is determined on the reception side that the transmission is performed, and input (reception) of the transmitted data is performed.
In a data communication method utilizing such transmission path, it is necessary to detect that a communication state is not normal due to an unconnected state on the transmission side, disconnection of the transmission path, failure on the transmission side or others. For detecting such state of the transmission path, a signal detecting circuit is used to determine whether an amplitude of a signal delivered to the reception side is kept smaller than a predetermined value for at least a predetermined time, or more.
In the transmission method, in which a signal line is kept at the reference voltage level when no signal is transmitted, and a signal line potential changes when the data is transmitted, it is necessary to discriminate between a no-signal state and a signal-transmission state for establishing data synchronization.
A patent reference 1 (Japanese Patent Laying-Open No. 2000-083069) has disclosed an example of a signal detecting circuit for detecting such states of a transmission path. In the construction disclosed in the patent reference 1, cross-coupled MOS transistors (insulated gate field effect transistors) are provided between signal lines (a pair of complementary signal lines) transmitting a differential signal and an internal signal detecting node. More specifically, one of the MOS transistors has a gate and a source connected to first and second signal lines forming the complementary signal lines, respectively. The other MOS transistor has a gate and a source connected to the second and first signal lines, respectively. In a no-signal state, the signal detection node is precharged to a level of e.g., a high-side power supply voltage Vh equal to a power supply voltage.
In the no-signal state, the paired complementary signal lines are both kept at a voltage level of an intermediate voltage ((Vh+V1)/2) intermediate between high and low-side power supply voltages Vh and V1. Accordingly, in the no-signal state, the cross-coupled MOS transistors each have the same potential at the source and gate thereof, and are kept off, so that no current flows through the cross-coupled MOS transistors. In the signal transmission, a voltage difference is caused between the first and second signal lines transmitting the differential signal. Thus, a current flows through one of the cross-coupled MOS transistors to change the potential of the signal detecting node. By detecting the voltage change on the signal detecting node or the flowing of the current, the signal receiving state is detected, and the input current is driven.
According to the construction disclosed in the patent reference 1, the transmission side alternately attains a data transmission state and an output high-impedance state in a cycle of a half cycle period of a clock signal. In one clock cycle, therefore, the complementary signal line pair is driven according to transmission data only for a time period of half the clock cycle. On the reception side, the voltage difference between the complementary signal lines is detected using the cross-coupled MOS transistors, and a signal reception detection signal is produced. An input circuit is made active in synchronization with that signal reception detection signal, to take in the received signal. Alternatively, an internally provided clock generating circuit is activated during the signal reception period, and first and subsequent data of received data string is taken-in in synchronization with an internal clock signal generated by the internal clock generating circuit.
By using the signal detecting circuit of the patent reference 1, it may be possible to determine whether the signal lines transmitting the differential signal are in the no-signal state.
When digital signals are to be transmitted and received at a high speed with low power consumption, it is desired to minimize an amplitude of a transmission signal. When the construction disclosed in the patent reference 1 is used for detecting the differential signal of such a minute amplitude, it is necessary to make the threshold voltages of cross-coupled differential MOS transistors as low as possible. Therefore, the MOS transistors for the reception detection must be made different in threshold voltages from MOS transistors of other circuitry, so that a problem of increase of manufacturing steps and therefore increase of cost arise.
First and second signal lines of the complementary signal line pair transmitting the differential signal are coupled to the source nodes of the cross-coupled first and second MOS transistors, respectively. Also, the first and second signal lines are connected to gates of the second and first transistors, respectively. In the signal transmission, therefore, when the first and second signal lines are at the high- and low-levels, respectively, the second MOS transistor is turned on to conduct a current to the second signal line. This current supplied from the second MOS transistor acts to reduce the amplitude (the minute amplitude) of the differential signal, and it may be impossible to detect accurately the received signal. Particularly, in the case when the signal detecting MOS transistors drive both the first and second signal lines to the high side in the data receiving, even when the first and second signal lines are short-circuited to be equalized in potential, the reference voltage could not return to the original intermediate voltage of (Vh+V1)/2, and the reference voltage shifts toward high-side voltage Vh. This state causes a problem that the received signal can no longer be detected accurately.
In the construction disclosed in the patent reference 1, each of the threshold voltages of the cross-coupled MOS transistors defines the detectable amplitude of the differential signal. In this case, the detectable signal amplitude is fixed. Therefore, when the signal amplitude changes, e.g., due to change in interface specification, a signal detecting circuit must be redesigned and re-manufactured.
Further, when a failure in data transmission path for transmission and reception is to be detected through the no-signal state, a criterion for such failure detection cannot be set flexibly depending on a use environment. The patent reference 1 discusses a construction for establishing the synchronization of the transmission data by detecting the voltage level of the signal transmission path, but does not consider a construction for detecting a failure in a signal line of the transmission path.